While machine translation has greatly improved, an embedded lightweight energy-efficient hardware remains elusive because existing solutions based on artificial neural networks (NNs) are computation-intensive and energy-hungry requiring server-based implementations, which also raises data protection and privacy concerns. Today, 2D electronic architectures suffer from "unscalable" interconnects, making it difficult for them to compete with biological neural systems in terms of real-time information-processing capabilities with comparable energy consumption. Recent advances in materials science, device technology and synaptic architectures have the potential to fill this gap with novel disruptive technologies that go beyond conventional CMOS technology. A promising solution comes from vertical nanowire field-effect transistors (VNWFETs) to unlock the full potential of truly 3D neuromorphic computing performance and density. Through actual VNWFETs fabrication setting up a design-technology co-optimization approach, the FULLMONTI vision is to develop regular 3D stacked hardware layers of NNs empowering the most efficient machine translation thanks to a fine-grain hardware / software co-optimisation. FULLMONTI consortium is a strong partnership with complementary expertise and extensive track-records in the fields of nanoelectronics, unconventional logic design, reliability, system‐level design, machine translation, cognition sciences. The consortium is composed of 50% of junior researchers and 90% of first-time participants to FETPROACT.  

FVLLMONTI is organized around 4 specific objectives (OBJ) targeting 12 Key Performance Indicators (KPI) mastered through 16 Milestones (MS):

Objective 1: Compactness: From fabricated low-complexity hardware to minimal neural network compute cube (N2C2)

Specific objective 1 (OBJ1) concentrates on the compactness of the elements in the FVLLMONTI value chain from low-level logic blocks up to a critical compute function in N2C2 to ensure the computation resource footprint.

Objective 2: Performance: Energy-delay-product assessment of the computational layer, the embedded Non-Volatile Memory (e-NVM) and interconnects

Specific Objective 2 (OBJ2) is designed to quantify the conventional figure-of-merit energy-delay-product (EDP) towards fast and ultra-low-power data transfer between the e-NVM using ferroelectric-gated VNWFET and the computing layer, thereby addressing the whole FVLLMONTI value chain from low-level logic blocks up to a critical compute function in N2C2.

Objective 3: Validation of the VNWFET technology for live English-French streaming speech recognition to text

Specific Objective 3 (OBJ3) focuses on exploring the use of VNWFET-based 3D logic cells and e-NVM blocks in multiple layers of NNs enabling ultra-compact and energy-efficient Transformers NNs for Automatic Speech Recognition (ASR) and Machine translation (MT). Their compactness and EDP will be compared with general-purpose architectures with CNN accelerators. To validate the approach, the target application is live English-French streaming speech recognition to text.

Objective 4: 3D NN architecture robustness

Specific Objective 4 (OBJ4) assesses the reliability of VNWFET devices at the early step of their development. The impact of the identified wear out failure mechanisms will be appraised on the whole FVLLMONTI value chain: N2C2, 3D NN architecture and up to the ASR and MT application. Beyond the specific translation application, the final intent is to demonstrate the intrinsic 3D NN architecture robustness.

KPI4: EDP assessment for JL VNWFETs, ION of at least 300 µA/µm at a supply voltage below 0.9V with scaled gate length

KPI5: EDP assessment for PC VNWFETs, ION of at least 10 µA/µm at a supply voltage below 2 V

KPI6: EDP assessment for read and write operation of a single transistor ferroelectric VNWFET cell with 3 V write voltage and 2 V operation voltage or below

KPI7: EDP assessment of 1-bit FA designs exploiting reconfigurability and/or e-NVM function

KPI8: NN compression size

KPI9: For ASR and MT 

KPI10: Word Error Rate (WER) on read English and French

KPI11: Bi-Lingual Evaluation Understudy (BLEU) score

KPI12: Intrinsic 3D NN architecture robustness, irrespective of the application: Architectural Vulnerability Factor (AVF)  

partners / contact

UNIVERSITE DE BORDEAUX

[ UBx ]

France

Cristell MANEUX

Cristell MANEUX

Project Coordinator. Full Professor at IMS Laboratory, Department of Sciences and Engineering, University of Bordeaux, France.

CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE CNRS

[ CNRS-LAAS ]

France

Guilhem LARRIEU

Guilhem LARRIEU

WP1 Leader. Research Director at Laboratory for Analysis and Architecture of Systems, CNRS-LAAS, France.

ECOLE CENTRALE DE LYON

[ ECL-INL ]

France

Ian O'Connor

Ian O'Connor

WP4 Leader. Distinguished Professor at Ecole Centrale de Lyon, France.

GLOBAL TCAD SOLUTIONS GMBH

[ GTS ]

Austria

Oskar BAUMGARTNER

Oskar BAUMGARTNER

WP3 Leader. Chief Operating Officer at Global TCAD Solutions GmbH, Austria.

ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE

[ EPFL ]

Switzerland

David ATIENZA

David ATIENZA

WP5 Leader. Professor and Director of Embedded Systems Laboratory, EPFL, Switzerland.

NAMLAB GGMBH

[ NLB ]

Germany

Jens TROMMER

Jens TROMMER

WP6 Leader. Senior Scientist Emerging Devices at NaMLab gGmbH, Germany.

This project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 101016776.

graph - chart

Start 01/01/2021
20% 29/11/2021
End 28/02/2025
Budget allocation . M€ Budget allocation
Effort 637 p*m Effort
Effort 13 persons Full time equivalent

news

Workshop at the HiPEAC Computing System Week

2021-10-26

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1st Advisory Board meeting (Bordeaux, France)

2021-06-21

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Invited paper at IEDM 2021, the 67th Annual International Electron Devices Meeting

2021-06-14

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Video recording available for FVLLMONTI presentation at NEUROTECH

2021-05-10

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NEUROTECH online event

2021-04-26

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events

2021-03-09

Project management plenary meeting

2021-02-25

Kick-off FVLLMONTI project

publications

3D Logic Cells Design and Results Based on Ve...

2021-01-01

Mukherjee, C., Deng, M., Marc, F., Maneux, C., Poittevin, A., O'Connor, I., Beux, S.L., Marchand, C., Kumar, A., Lecestre, A., Larrieu,G...

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Single-step reactive ion etching process for ...

2021-01-01

Tom Mauersberger, Jens Trommer, Saurabh Sharma, Martin Knaut, Darius Pohl, Bernd Rellinghaus, Thomas Mikolajick, André Heinzig

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Patterning and integration issues of doped na...

2021-01-01

Abhishek Kumar, Aurélie Lecestre, Jonas Müller , Guilhem Larrieu

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Modelling of vertical and ferroelectric junct...

2021-01-01

C. Maneux, C. Mukherjee, M. Deng, M. Dubourg, L. Reveil, G. Bordea, A. Lecestre, G. Larrieu, J. Trommer, E.T. Breyer, S. Slesazeck, T. Mikol...

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Compact Modeling of 3D Vertical Junctionless ...

2021-01-01

Mukherjee, C., Larrieu, G., Maneux, C. 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration o...

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3D Logic Cells Design and Results Based on Ve...

2021-01-01

Poittevin, A., Mukherjee, C., O’Connor, I., Maneux, C., Larrieu, G., Deng, M., Le Beux, S., Marc, F., Lecestre, A., Marchand, C., Kuma...

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Compact modeling of 3D vertical junctionless ...

2021-01-01

Mukherjee, C., Poittevin, A., O'Connor, I., Larrieu, G., Maneux, C.Solid-State Electronics, 183, art. no. 108125.

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